boards/arm/v2m_musca_b1/doc/index.rst
.. zephyr:board:: v2m_musca_b1
ARM V2M Musca B1 ################
Overview
The v2m_musca_b1 board configuration is used by Zephyr applications that run on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M33 CPU and the following devices:
.. image:: img/v2m_musca_b1.jpg :align: center :alt: ARM V2M Musca B1
More information about the board can be found at the V2M Musca B1 Website_.
Hardware
ARM V2M MUSCA B1 provides the following hardware components:
ARM Cortex-M33
ARM IoT Subsystem for Cortex-M33
Memory
Debug
Arduino interface
On-board Peripherals
The v2m_musca_b1 board provides the following user push buttons:
.. zephyr:board-supported-hw::
Musca B1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
A Cortex-M33-based board uses vectored exceptions. This means each exception calls a handler directly from the vector table.
Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed in the following table:
+------+------------+----------------+--------------------------+ | Exc# | Name | Remarks | Used by Zephyr Kernel | +======+============+================+==========================+ | 1 | Reset | | system initialization | +------+------------+----------------+--------------------------+ | 2 | NMI | | system fatal error | +------+------------+----------------+--------------------------+ | 3 | Hard fault | | system fatal error | +------+------------+----------------+--------------------------+ | 4 | MemManage | MPU fault | system fatal error | +------+------------+----------------+--------------------------+ | 5 | Bus | | system fatal error | +------+------------+----------------+--------------------------+ | 6 | Usage | Undefined | system fatal error | | | fault | instruction, | | | | | or switch | | | | | attempt to ARM | | | | | mode | | +------+------------+----------------+--------------------------+ | 7 | SecureFault| Unauthorized | system fatal error | | | | access to | | | | | secure region | | | | | from ns space | | +------+------------+----------------+--------------------------+ | 8 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 9 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 10 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 11 | SVC | | system calls, kernel | | | | | run-time exceptions, | | | | | and IRQ offloading | +------+------------+----------------+--------------------------+ | 12 | Debug | | system fatal error | | | monitor | | | +------+------------+----------------+--------------------------+ | 13 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 14 | PendSV | | context switch | +------+------------+----------------+--------------------------+ | 15 | SYSTICK | | system clock | +------+------------+----------------+--------------------------+ | 16 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 17 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 18 | Reserved | | not handled | +------+------------+----------------+--------------------------+
The ARM V2M Musca B1 Board has 4 GPIO controllers. These controllers are responsible for pin-muxing, input/output, pull-up, etc.
All GPIO controller pins are exposed via the following sequence of pin numbers:
Mapping from the ARM V2M Musca B1 Board pins to GPIO controllers:
.. rst-class:: rst-columns
Peripheral Mapping:
.. rst-class:: rst-columns
For more details please refer to Musca B1 Technical Reference Manual (TRM)_.
Musca B1 has a built-in RGB LED connected to GPIO[4:2] pins.
.. note:: The SCC registers select the functions of pins GPIO[4:2].
V2M Musca B1 has a 32.768kHz crystal clock. The clock goes to a PLL and is multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The default is 40MHz but can be increased to 160MHz maximum for the secondary processor (CPU1) via software configuration. The maximum clock frequency for the primary processor (CPU0) is 40MHz.
The ARM Musca B1 processor has two UARTs. Both the UARTs have only two wires for RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by default, uses UART1.
IDAU_). The IDAU is used to define
secure and non-secure memory maps. By default, all of the memory space is
defined to be secure accessible only.AMBA®_ interconnect.The ARM Musca B1 test chip implements a Serial Configuration Control (SCC) register. The purpose of this register is to allow individual control of clocks, reset-signals and interrupts to peripherals, and pin-muxing.
Normal Musca-B1 test chip boot operation is from 4MB eFlash by default, and it offers the fastest boot method. Musca-B1 test chip also support to boot from 8MB QSPI. You can update the DAPLink firmware for either QSPI or eFlash for booting.
Programming and Debugging
Musca B1 supports the v8m security extension, and by default boots to the secure state.
When building a secure/non-secure application, the secure application will have to set the idau/sau and mpc configuration to permit access from the non-secure application before jumping.
The following system components are required to be properly configured during the secure firmware:
For more details please refer to Corelink SSE-200 Subsystem_.
V2M Musca B1 provides:
This interfaces are exposed via DAPLink which provides:
For more details please refer
to the DAPLink Website_.
You can build applications in the usual way. Here is an example for
the :zephyr:code-sample:hello_world application.
.. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: v2m_musca_b1 :goals: build
Open a serial terminal (minicom, putty, etc.) with the following settings:
Reset the board, and you should see the following message on the corresponding serial port:
.. code-block:: console
Hello World! musca_b1
The process requires five steps:
In order to build tfm please refer to Trusted Firmware M Guide_.
Follow the build steps for AN521 target while replacing the platform with
-DTARGET_PLATFORM=MUSCA_B1 and compiler (if required) with -DCOMPILER=GNUARM
Copy over tfm as a library to the Zephyr project source and create a shortcut for the secure veneers and necessary header files. All files are in the install folder after TF-M built.
Applications must be converted to Intel's hex format before being flashed to a V2M Musca B1. An optional bootloader can be prepended to the image. The QSPI flash base address alias is 0x0, and the eFlash base address alias is 0xA000000. The image offset is calculated by adding the flash offset to the bootloader partition size.
A third-party tool (srecord) is used to generate the Intel formatted hex image.
For more information refer to the Srecord Manual_.
.. code-block:: bash
srec_cat $BIN_BOOTLOADER -Binary -offset $FLASH_OFFSET $BIN_SNS -Binary -offset $IMAGE_OFFSET -o $HEX_FLASHABLE -Intel
srec_cat $BIN_BOOTLOADER -Binary -offset 0xA000000 $BIN_SNS -Binary -offset 0xA020000 -o $HEX_FLASHABLE -Intel
Connect the V2M Musca B1 to your host computer using the USB port. You should
see a USB connection exposing a Mass Storage (MUSCA_B) and a USB Serial Port.
Copy the generated zephyr.hex in the MUSCA_B drive.
Reset the board, and you should see the following message on the corresponding serial port:
.. code-block:: console
Hello World! musca_b1
.. _V2M Musca B1 Website: https://developer.arm.com/Tools%20and%20Software/Musca-B1%20Test%20Chip%20Board
.. _Musca B1 Technical Reference Manual (TRM): https://developer.arm.com/documentation/101312/latest/
.. _DAPLink Website: https://github.com/ARMmbed/DAPLink
.. _Cortex M33 Generic User Guide: https://developer.arm.com/documentation/100235/latest/
.. _Trusted Firmware M Guide: https://tf-m.docs.trustedfirmware.org/en/latest/building/tfm_build_instruction.html
.. _Corelink SSE-200 Subsystem: https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
.. _Srecord Manual: https://srecord.sourceforge.net/man/man1/srec_cat.1.html
.. _IDAU: https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU-
.. _AMBA®: https://developer.arm.com/products/architecture/system-architectures/amba