boards/arm/mps2/doc/mps2_an521.rst
.. _mps2_an521_board:
ARM MPS2+ AN521 ###############
Overview
The mps2/an521 board configuration is used by Zephyr applications that run on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 CPU and the following devices:
.. image:: img/mps2.jpg :align: center :alt: ARM MPS2+ AN521
In addition to enabling actual hardware usage, this board configuration can also use QEMU to emulate the AN521 platform running on the MPS2+.
More information about the board can be found at the MPS2 FPGA Website_.
.. note:: This board configuration makes no claims about its suitability for use with actual MPS2 hardware systems using AN521, or any other hardware system. It has been tested on actual hardware, but its primary purpose is for use with QEMU and unit tests for the ARM Cortex-M33.
The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores (CPU0 and CPU1). Zephyr provides support for building firmware images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions both Secure and Non-Secure firmware images may be built.
The BOARD options are summarized below:
+----------------------+-------------------------------------------------------+ | BOARD | Description | +======================+=======================================================+ | mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 | +----------------------+-------------------------------------------------------+ | mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 | +----------------------+-------------------------------------------------------+ | mps2/an521/cpu1 | For building firmware on CPU1 | +----------------------+-------------------------------------------------------+
The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory regions are shared across both cores, and are aliased in both secure and non-secure regions, where the secure memory alias has an offset of 0x10000000 relative to non-secure.
The following memory map and partitioning schemes are used by default, where the offset value is the offset from the base of the 4MB code or SRAM block, ignoring the S/NS alias difference.
+-------------------------+-----+----------------+----------------+------------+ | Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | +=========================+=====+================+================+============+ | mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S | +-------------------------+-----+----------------+----------------+------------+ | mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | +-------------------------+-----+----------------+----------------+------------+ | mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | +-------------------------+-----+----------------+----------------+------------+
The mps2/an521/cpu0/ns board target is intended to be used with TF-M, with the
Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M
boots the secure processing environment before initialising Zephyr in the
non-secure processing environment. The non-secure Zephyr image is offset to
make room for the secure bootloader, and the secure firmware (TF-M), resulting
in a starting address of 0x00100000. SRAM begins with a 1MB offset at
0x28100000.
The mps2/an521/cpu1 board target is setup for the second core on the
AN521, using the final 468KB code memory in the 4MB code block. This value
is chosen to maintain compatibility with TF-M, which marks that final 468KB
code region as Unused. Code memory thus starts with an offset of
3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB
(address 0x28180000).
This memory map enables the two alternative board targets to be used together if required, at the cost of reducing the amount of code memory available on the second core to the worst-case scenario from TF-M.
When using one of the alternative board targets (mps2/an521/cpu0/ns or
mps2/an521/cpu1), care needs to be taken with the amount of code or
SRAM memory used on the primary board target (mps2/an521) since there is
some overlap in the memory maps.
Hardware
ARM MPS2+ AN521 provides the following hardware components:
Dual core ARM Cortex-M33
Soft Macro Model (SMM) implementation of SSE-200 subsystem
Memory
Debug
Interface
On-board Peripherals
The mps2/an521 board provides the following user push buttons:
mps2 for details.MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
A Cortex-M33-based board uses vectored exceptions. This means each exception calls a handler directly from the vector table.
Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed in the following table:
+------+------------+----------------+--------------------------+ | Exc# | Name | Remarks | Used by Zephyr Kernel | +======+============+================+==========================+ | 1 | Reset | | system initialization | +------+------------+----------------+--------------------------+ | 2 | NMI | | system fatal error | +------+------------+----------------+--------------------------+ | 3 | Hard fault | | system fatal error | +------+------------+----------------+--------------------------+ | 4 | MemManage | MPU fault | system fatal error | +------+------------+----------------+--------------------------+ | 5 | Bus | | system fatal error | +------+------------+----------------+--------------------------+ | 6 | Usage | Undefined | system fatal error | | | fault | instruction, | | | | | or switch | | | | | attempt to ARM | | | | | mode | | +------+------------+----------------+--------------------------+ | 7 | SecureFault| Unauthorized | system fatal error | | | | access to | | | | | secure region | | | | | from ns space | | +------+------------+----------------+--------------------------+ | 8 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 9 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 10 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 11 | SVC | | system calls, kernel | | | | | run-time exceptions, | | | | | and IRQ offloading | +------+------------+----------------+--------------------------+ | 12 | Debug | | system fatal error | | | monitor | | | +------+------------+----------------+--------------------------+ | 13 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 14 | PendSV | | context switch | +------+------------+----------------+--------------------------+ | 15 | SYSTICK | | system clock | +------+------------+----------------+--------------------------+ | 16 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 17 | Reserved | | not handled | +------+------------+----------------+--------------------------+ | 18 | Reserved | | not handled | +------+------------+----------------+--------------------------+
The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 bits of IO. These controllers are responsible for pin-muxing, input/output, pull-up, etc.
All GPIO controller pins are exposed via the following sequence of pin numbers:
Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers:
.. rst-class:: rst-columns
Peripheral Mapping:
.. rst-class:: rst-columns
For more details refer to MPS2+ AN521 Technical Reference Manual (TRM)_.
MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC).
.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON.
MPS2+ AN521 has several clocks connected:
.. rst-class:: rst-columns
The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses UART0, which is J10 on the board.
UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports.
IDAU_). The IDAU is used to define
secure and non-secure memory maps. By default, all of the memory space is
defined to be secure accessible onlyAMBA®_ interconnectThe MPS2+ AN521 implements a Serial Configuration Control (SCC) register. The purpose of this register is to allow individual control of clocks, reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and switches.
Programming and Debugging
MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. Applications built for the mps2/an521 board by default boot in the Secure state.
MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension.
Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure
firmware image. The Secure image can be built using either Zephyr
or Trusted Firmware M_ (TF-M). Non-Secure firmware images are always built
using Zephyr. The two alternatives are described below.
.. note::
By default the Secure image for the MPS2+ AN521 (CPU0) is built using TF-M.
The process to build the Secure firmware image using TF-M and the Non-Secure firmware image using Zephyr requires the following steps:
Build the Non-Secure Zephyr application
for MPS2+ AN521 (CPU0) using -DBOARD=mps2/an521/cpu0/ns.
To invoke the building of TF-M the Zephyr build system requires the
Kconfig option BUILD_WITH_TFM to be enabled, which is done by
default when building Zephyr as a Non-Secure application.
The Zephyr build system will perform the following steps automatically:
.. note::
Depending on the TF-M configuration, an application DTS overlay may be required, to adjust the Non-Secure image Flash and SRAM starting address and sizes.
The process to build the Secure and the Non-Secure firmware images using Zephyr requires the following steps:
-DBOARD=mps2/an521 and
CONFIG_TRUSTED_EXECUTION_SECURE=y and CONFIG_BUILD_WITH_TFM=n
in the application project configuration file.-DBOARD=mps2/an521/cpu0/ns.Build the Zephyr app in the usual way (see :ref:build_an_application
and :ref:application_run), using -DBOARD=mps2/an521 for
the firmware running on the MPS2+ AN521 (CPU0).
When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), the Secure application will have to set the SAU/IDAU configuration to allow Non-Secure access to all CPU resources utilized by the Non-Secure application firmware. SAU/IDAU configuration shall take place before jumping to the Non-Secure application.
The following system components are required to be properly configured during the secure firmware:
For more details refer to Corelink SSE-200 Subsystem_.
Applications may be built for the second Cortex-M33 (remote) core of MPS2+ AN521. The core is referred to as CPU1.
Build the Zephyr app in the usual way (see :ref:build_an_application
and :ref:application_run), using -DBOARD=mps2/an521/cpu1 for
the firmware running on the MPS2+ AN521 (CPU1).
The Zephyr build will automatically trigger building a minimal (empty) secure-only firmware for CPU0, which will be used to boot the remote core (CPU1).
MPS2+ AN521 provides:
Build applications as described above.
Here is an example for the :zephyr:code-sample:hello_world application built as
a secure-only application for CPU0.
.. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: mps2/an521 :goals: build
Open a serial terminal (minicom, putty, etc.) with the following settings:
Reset the board, and you should see the following message on the corresponding serial port:
.. code-block:: console
Hello World! mps2_an521
Applications can be in elf, hex or bin format. The binaries are flashed when the board boots up, using files stored on the on-board Micro SD card. The Motherboard Configuration Controller (MCC) is responsible for loading the FPGA image and binaries.
Connect the MPS2+ to your host computer using the USB port. You should see a
USB connection exposing a Mass Storage (V2M_MPS2 by default).
The update requires 3 steps:
<MPS2 device name>/SOFTWARE/.<MPS2 device name>/MB/HBI0263C/AN521/images.txt.AN521/images.txt file as follows:.. code-block:: bash
TITLE: Versatile Express Images Configuration File
[IMAGES] TOTALIMAGES: 1 ;Number of Images (Max: 32)
IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program
IMAGE0FILE: \SOFTWARE\zephyr.bin
Reset the board, and you should see the following message on the corresponding serial port:
.. code-block:: console
Hello World! mps2_an521
.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario.
.. _MPS2 FPGA Website: https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2
.. _MPS2+ AN521 Technical Reference Manual (TRM): https://developer.arm.com/documentation/dai0521/latest/
.. _Cortex M33 Generic User Guide: https://developer.arm.com/documentation/100235/latest/
.. _Trusted Firmware M: https://tf-m.docs.trustedfirmware.org/en/latest/building/tfm_build_instruction.html
.. _Corelink SSE-200 Subsystem: https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
.. _IDAU: https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU-
.. _AMBA®: https://developer.arm.com/products/architecture/system-architectures/amba