Tock OT Notes 4/30/2020

Present:

• Brad Campbell (Chair), University of Virginia
• Jon Flatley, Google
• Silvestrs Timofejevs, lowRISC
• Johnathan Van Why, Google
• Garret Kelly, Google
• Alistair Francis, Western Digital
• Phil Levis, Stanford

Updates

• Silvestrs: Updated work on conditional compilation. Passes CI. Ready for review.
• Brad: Hopefully 1.5 will be merged today. Then can resume merging PRs.
• Alistair: Working on OT and apps on QEMU. Goal: automated testing of PRs with QEMU.
• Sent out updates to QEMU on mailing list.
  • Support for Ibex PLIC and UART, plus connecting those peripherals to the main chip.
• Garret: What does the maintenance look like for Ibex on QEMU? The chip is changing, which version should QEMU match?
• Alistair: UART is easy to keep up with any changes. Hopefully the PLIC becomes standards compliant and therefore can use the default version.
• Brad: Tested tock on Arty-e21 board, minor fixes needed but otherwise working as expected.

PMP

• Silvestrs: Why remove the "power of 2" check in the PMP implementation?

• Alistair: That check is left over from the NAPOT implementation. With Top-of-Range now it is not longer needed.

• Garret: ToR for OT will require 32 byte alignment.

• Alistair: I think that is standards compliant.

• Brad: Using that as a default is probably fine, even if not required. Not a huge overhead.

• Phil: There might be alignment issues with memory protection more generally.

• ARM has a standard, but some chips implemented their own version.

• What is the outlook for PMP? Will we see a number of custom implementations?

• Garret: I would expect that SiFive would stick the spec.

• New RISC-V specs have been slow to be release, so I don't necessarily expect it to change any time soon.

• Alistair: Probably won't see a lot of custom implementations. Instead, there may be spec extensions (like for the core) where peripherals like the PMP can be customized but still standards compliant.

• Garret: Well, OT is looking to use a non-compliant version that has additional lock bits.

• Phil: ARM you have to buy IP, presents a barrier.

• Alistair: I think with RISC-V the trademark restriction would make it so a non-spec version couldn't be called "RISC-V".

• Garret: But the PMP is optional, so it could be a RISC-V core without a PMP, and instead has an "OTPMP" which is different.

• Garret: PMP currently too restrictive. Only 16 regions (8 effectively for ToR). Use 6 regions for secure boot, not enough remaining.

• Alistair: What about the extended PMP spec?

• Garret: Is that out?

• What happens with the hardware diversity?

• Brad: Probably have to just embrace it.

• Garret: Tock abstractions help.

• Brad: Tricky part is finding bugs twice.

• Phil: With variations in hardware there isn't much we can do.

libtock-rs

• Johnathan: Not much change.

OT PRs

• Phil: Are they ready, just waiting for 1.5?
• Alistair: Yes. Should be ready or close to ready.
• Phil: OK I can take a look.

HMAC

• Phil: Key size issue. If variable key size, then setting the key must be asynchronous. To avoid that complexity, better to fix the size for now.
• But, certain implementations could use DMA (or something) to set the key, so this may still have to change.