Doc Esp32s3.Doc

@defgroup cpu_esp32_esp32s3 ESP32-S3 family @ingroup cpu_esp32 @brief Specific properties of ESP32-S3 variant (family) @author Gunar Schorcht [email protected]

\section esp32_riot_esp32s3 Specific properties of ESP32-S3 variant (family)

Embedded Flash and SPI RAM {#esp32_embedded_flash_ram_esp32s3}

There are many different versions of the ESP32-S3 chip and ESP32-S3 modules used on ESP32-S3 boards. They differ in the size of embedded Flash and SPI RAM as well as used SPI mode for Flash and SPI RAM. These differences allow dozens of different versions of a board. For example, there are 8 versions of the ESP32-S3 DevKitC-1 board with different flash and SPI RAM sizes.

Depending on the chip or module used, it has to be specified as a feature in the board definition whether SPI RAM is available (feature \ref esp32_spi_ram "esp_spi_ram") and whether Octal SPI Mode is used for the SPI RAM (feature \ref esp32_spi_ram "esp_spi_oct").

If the feature esp_spi_ram is given, the SPI RAM can be used as heap by using the pseudo module esp_spi_ram.

If Quad SPI mode is used, GPIO26 ... GPIO32 are occupied and cannot be used for other purposes. In case of Octal SPI mode, the pseudomodule esp_spi_oct is additionally enabled and GPIO33 ... GPIO37 are occupied if the SPI RAM is enabled by using the pseudomodule esp_spi_ram. GPIO33 ... GPIO37 are then not available for other purposes. Conflicts may occur when using these GPIOs.

GPIO pins {#esp32_gpio_pins_esp32s3}

ESP32-S3 has 45 GPIO pins, where a subset can be used as ADC channel and as low-power digital input/output in deep-sleep mode, the so-called RTC GPIOs. Some of them are used by special SoC components and are not broken out on all ESP32-S3 modules. The following table gives a short overview.

<b>ADC:</b> Pins that can be used as ADC channels.

<b>RTC:</b> Pins that are RTC GPIOs and can be used in deep-sleep mode.

<b>PU/PD:</b> Pins that have software configurable pull-up/pull-down functionality.

Strapping pins {#esp32_gpio_pins_esp32s3_strapping}

GPIO0, GPIO3, GPIO45 and GPIO46 are bootstrapping. GPIO0 and GPIO46 pins are used to boot ESP32-S3 in different modes:

If EFUSE_STRAP_JTAG_SEL is set, GPIO3 is used to select the interface that is used as JTAG interface.

@note If EFUSE_DIS_USB_JTAG or EFUSE_DIS_PAD_JTAG are set, the interface selection is fixed and GPIO3 is not used as bootstrapping pin.

GPIO45 is used to select the voltage VDD_SPI for the Flash/PSRAM interfaces SPI0 and SPI1.

ADC Channels {#esp32_adc_channels_esp32s3}

ESP32-S3 integrates two 12-bit ADCs (ADC1 and ADC2) with 20 channels in total:

• ADC1 supports 10 channels: GPIO1 ... GPIO10
• ADC2 supports 10 channels: GPIO11 ... GPIO20

@note

• ADC2 is also used by the WiFi module. The GPIOs connected to ADC2 are therefore not available as ADC channels if the modules esp_wifi or esp_now are used.
• GPIO3 is a strapping pin und shouldn't be used as ADC channel

I2C Interfaces {#esp32_i2c_interfaces_esp32s3}

ESP32-S3 has two built-in I2C interfaces.

The following table shows the default configuration of I2C interfaces used for ESP32-S3 boards. It can be overridden by application-specific configurations.

PWM Channels {#esp32_pwm_channels_esp32s3}

The ESP32-S3 LEDC module has 1 channel group with 8 channels. Each of these channels can be clocked by one of the 4 timers.

SDMMC Interfaces {#esp32_sdmmc_interfaces_esp32s3}

The ESP32-S3 variant uses the GPIO matrix (i.e. SOC_SDMMC_USE_GPIO_MATRIX is defined in the SoC Capabilities file) to route the SDMMC signals to arbitrary pins. The GPIOs used for the SDMMC signals are therefore configurable and have to be defined in the board-specific configuration in array @ref sdmmc_config in addition to the used slot.

The width of the data bus used is determined by the GPIOs defined for the DAT lines. To use a 1-bit data bus, only DAT0 (@ref sdmmc_conf_t::dat0) must be defined. All other GPIOs for the DAT lines must be set undefined (@ref GPIO_UNDEF). For a 4-bit data bus, the GPIOs for pins DAT1 to DAT3 (@ref sdmmc_conf_t::dat1 ... @ref sdmmc_conf_t::dat3) must also be defined. An 8-bit data bus width requires the definition of DAT4 to DAT7 (@ref sdmmc_conf_t::dat4 ... @ref sdmmc_conf_t::dat7) and the enabling of the periph_sdmmc_8bit module.

The following example shows a configuration with 4-bit or 8-bit data bus width dependent on whether the periph_sdmmc_8bit module is enabled.

static const sdmmc_conf_t sdmmc_config[] = {
    {
        .slot = SDMMC_SLOT_0,
        .cd = GPIO16,
        .wp = GPIO_UNDEF,
        .clk = GPIO14,
        .cmd = GPIO15,
        .dat0 = GPIO2,
        .dat1 = GPIO4,
        .dat2 = GPIO12,
        .dat3 = GPIO13,
#if IS_USED(MODULE_PERIPH_SMMC_8BIT)
        .dat4 = GPIO33,
        .dat5 = GPIO33,
        .dat6 = GPIO33,
        .dat7 = GPIO33,
#endif
    },
};

#define SDMMC_NUMOF 1

If the board supports a Card Detect pin or a Write Protect pin, the corresponding GPIOs have to be defined in @ref sdmmc_conf_t::cd and @ref sdmmc_conf_t::wp. Otherwise they have to be set to undefined (@ref GPIO_UNDEF).

SPI Interfaces {#esp32_spi_interfaces_esp32s3}

ESP32-S3 has four SPI controllers where SPI0 and SPI1 share the same bus and can only operate in memory mode while SPI2 and SPI3 can be used as general purpose SPI:

• controller SPI0 is reserved for external memories like Flash and PSRAM
• controller SPI1 is reserved for external memories like Flash and PSRAM
• controller SPI2 can be used for peripherals (also called FSPI)
• controller SPI3 can be used for peripherals

Thus, SPI2 (FSPI) and SPI3 can be used as general purpose SPI in RIOT as SPI_DEV(0) and SPI_DEV(1) by defining the symbols SPI0_* and SPI1_*.

The following table shows the pin configuration used by default, even though it can vary from board to board.

Timers {#esp32_timers_esp32s3}

ESP32-S3 has two timer groups with two timers each, resulting in a total of four timers. Since one timer is used as system timer, up to three timers with one channel each can be used in RIOT as timer devices TIMER_DEV(0) ... TIMER_DEV(2).

Additionally ESP32-S3 has three CCOMPARE registers which can be used alternatively as timer devices TIMER_DEV(0) ... TIMER_DEV(2) can be used in RIOT if the module esp_hw_counter is enabled.

UART Interfaces {#esp32_uart_interfaces_esp32s3}

ESP32 integrates three UART interfaces. The following default pin configuration of UART interfaces as used by a most boards can be overridden by the application, see section [Application-Specific Configurations] (#esp32_application_specific_configurations).

JTAG Interface {#esp32_jtag_interface_esp32s3}

There are two options on how to use the JTAG interface on ESP32-S3:

1. Using the built-in USB-to-JTAG bridge connected to an USB cable as follows:

   USB Signal	ESP32-S3 Pin
   D- (white)	GPIO19
   D+ (green)	GPIO20
   V_Bus (red)	5V
   Ground (black)	GND

   @note This option requires that the USB D- and USB D+ signals are connected to the ESP32-S3 USB interface at GPIO19 and GPIO20.

2. Using an external JTAG adapter connected to the JTAG interface exposed to GPIOs as follows:

   JTAG Signal	ESP32S3 Pin
   TRST_N	CHIP_PU
   TDO	GPIO40 (MTDO)
   TDI	GPIO41 (MTDI)
   TCK	GPIO39 (MTCK)
   TMS	GPIO42 (MTMS)
   GND	GND

Using the built-in USB-to-JTAG is the default option, i.e. the JTAG interface of the ESP32-S3 is connected to the built-in USB-to-JTAG bridge. To use an external JTAG adapter, the JTAG interface of the ESP32-S3 has to be connected to the GPIOs as shown above. For this purpose eFuses have to be burned with the following command:

espefuse.py burn_efuse JTAG_SEL_ENABLE --port /dev/ttyUSB0

Once the eFuses are burned with this command and option JTAG_SEL_ENABLE, GPIO3 is used as a bootstrapping pin to choose between the two options. If GPIO3 is HIGH when ESP32-S3 is reset, the JTAG interface is connected to the built-in USB to JTAG bridge and the USB cable can be used for on-chip debugging. Otherwise, the JTAG interface is exposed to GPIO39 ... GPIO42 and an external JTAG adapter has to be used.

Alternatively, the integrated USB-to-JTAG bridge can be permanently disabled with the following command:

espefuse.py burn_efuse DIS_USB_JTAG --port /dev/ttyUSB0

Once the eFuses are burned with this command and option DIS_USB_JTAG, the JTAG interface is always exposed to GPIO4 ... GPIO7 and an external JTAG adapter has to be used.

@note Burning eFuses is an irreversible operation.

For more information about JTAG configuration for ESP32-S3, refer to the section [Configure Other JTAG Interface] (https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/configure-other-jtag.html) in the ESP-IDF documentation.