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2026.07-devel9.9 KB
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<!-- SPDX-FileCopyrightText: 2025 Gunar Schorcht SPDX-License-Identifier: LGPL-2.1-only -->

@defgroup cpu_esp32_esp32c3 ESP32-C3 family @ingroup cpu_esp32 @brief Specific properties of ESP32-C3 variant (family) @author Gunar Schorcht [email protected]

\section esp32_riot_esp32c3 Specific properties of ESP32-C3 variant (family)

GPIO pins {#esp32_gpio_pins_esp32c3}

ESP32-C3 has 22 GPIO pins, where a subset can be used as ADC channel and as low-power digital input/output in deep-sleep mode, the so-called RTC GPIOs. Some of them are used by special SoC components. The following table gives a short overview.

<center>
PinTypeADC / RTCPU / PDSpecial functionRemarks
GPIO0In/OutyesyesXTAL_32K_P-
GPIO1In/OutyesyesXTAL_32K_N-
GPIO2In/OutyesyesBootstrapping
GPIO3In/Outyesyes-
GPIO4In/OutyesyesMTMSJTAG interface
GPIO5In/OutyesyesMTDIJTAG interface
GPIO6In/Out-yesMTCKJTAG interface
GPIO7In/Out-yesMTDOJTAG interface
GPIO8In/Out-yes--
GPIO9In/Out-yes-Bootstrapping, pulled up
GPIO10In/Out-yes--
GPIO11In/Out-yesVDD_SPInot broken out
GPIO12In/Out-yesFlash SDIHDonly in qoutand qiomode, see section Flash Modes
GPIO13In/Out-yesFlash SPIWPonly in qoutand qiomode, see section Flash Modes
GPIO14In/Out-yesFlash SPICS0-
GPIO15In/Out-yesFlash SPICLK-
GPIO16In/Out-yesFlash SPID-
GPIO17In/Out-yesFlash SPIQ-
GPIO18In/Out-yes-USB-JTAG
GPIO19In/Out-yes-USB-JTAG
GPIO21In/Out-yesUART0 RXConsole
GPIO22In/Out-yesUART0 TXConsole
</center>

<b>ADC:</b> these pins can be used as ADC inputs

<b>RTC:</b> these pins are RTC GPIOs and can be used in deep-sleep mode

<b>PU/PD:</b> these pins have software configurable pull-up/pull-down functionality.

@note GPIOs that can be used as ADC channels are also available as low power digital inputs/outputs in deep sleep mode.

GPIO2, GPIO8 and GPIO9 are bootstrapping pins which are used to boot ESP32-C3 in different modes:

<center>
GPIO2GPIO8GPIO9Mode
1X1SPI Boot mode to boot the firmware from flash (default mode)
110Download Boot mode for flashing the firmware
</center>

ADC Channels {#esp32_adc_channels_esp32c3}

ESP32-C3 integrates two 12-bit ADCs (ADC1 and ADC2) with 6 channels in total:

  • ADC1 supports 5 channels: GPIO0, GPIO1, GPIO2, GPIO3 and GPIO4
  • ADC2 supports 1 channel: GPIO5 or internal signals such as vdd33

The maximum number of ADC channels #ADC_NUMOF_MAX is 6.

@note

  • According to the ESP32-C2 Errata Sheet, ADC2 with GPIO5 as ADC channel may not work correctly. By default it is still possible to use it anyway. Set CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 to 0 if you do not want to use it and want to activate the configuration check for this channel.
  • ADC2 is also used by the WiFi module. GPIO5 connected to ADC2 is therefore not available as ADC channels if the modules esp_wifi* or esp_now are used.

I2C Interfaces {#esp32_i2c_interfaces_esp32c3}

ESP32-C3 has one built-in I2C interfaces.

The following table shows the default configuration of I2C interfaces used for ESP32-C3 boards. It can be overridden by application-specific configurations.

<center>
DeviceSignalPinSymbolRemarks
I2C_DEV(0)#I2C0_SPEEDdefault is I2C_SPEED_FAST
I2C_DEV(0)SCLGPIO4#I2C0_SCL-
I2C_DEV(0)SDAGPIO5#I2C0_SDA-
</center>

PWM Channels {#esp32_pwm_channels_esp32c3}

The ESP32-C3 LEDC module has 1 channel groups with 6 channels. Each of these channels can be clocked by one of the 4 timers.

SPI Interfaces {#esp32_spi_interfaces_esp32c3}

ESP32-C3 has three SPI controllers where SPI0 and SPI1 share the same bus. They are used as interface for external memory and can only operate in memory mode:

  • Controller SPI0 is reserved for caching external memory like Flash
  • Controller SPI1 is reserved for external memory like PSRAM
  • Controller SPI2 can be used as general purpose SPI (also called FSPI)

Thus, only SPI2 (FSPI) can be used as general purpose SPI in RIOT as SPI_DEV(0).

The following table shows the pin configuration used for most boards, even though it can vary from board to board.

<center>
DeviceSignalPinSymbolRemarks
SPI0_HOST/SPI1_HOSTSPICS0GPIO14-reserved for flash and PSRAM
SPI0_HOST/SPI1_HOSTSPICLKGPIO15-reserved for flash and PSRAM
SPI0_HOST/SPI1_HOSTSPIDGPIO16-reserved for flash and PSRAM
SPI0_HOST/SPI1_HOSTSPIQGPIO17-reserved for flash and PSRAM
SPI0_HOST/SPI1_HOSTSPIHDGPIO12-reserved for flash and PSRAM (only in qio or qout mode)
SPI0_HOST/SPI1_HOSTSPIWPGPIO13-reserved for flash and PSRAM (only in qio or qout mode)
SPI2_HOST (FSPI)SCKGPIO6#SPI0_SCKcan be used
SPI2_HOST (FSPI)MOSIGPIO7#SPI0_MOSIcan be used
SPI2_HOST (FSPI)MISOGPIO2#SPI0_MISOcan be used
SPI2_HOST (FSPI)CS0GPIO10#SPI0_CS0can be used
</center>

Timers {#esp32_timers_esp32c3}

ESP32-C3 has two timer groups with one timer each, resulting in a total of two timers. Thus one timer with one channel can be used in RIOT as timer device TIMER_DEV(0), because one timer is used as system timer.

ESP32-C3 do not have CCOMPARE registers. The counter implementation can not be used.

UART Interfaces {#esp32_uart_interfaces_esp32c3}

ESP32 integrates three UART interfaces. The following default pin configuration of UART interfaces as used by a most boards can be overridden by the application, see section [Application-Specific Configurations] (#esp32_application_specific_configurations).

<center>
DeviceSignalPinSymbolRemarks
UART_DEV(0)TxDGPIO1#UART0_TXDcannot be changed
UART_DEV(0)RxDGPIO3#UART0_RXDcannot be changed
UART_DEV(1)TxDGPIO10#UART1_TXDoptional, can be overridden
UART_DEV(1)RxDGPIO9#UART1_RXDoptional, can be overridden
UART_DEV(2)TxDGPIO17UART2_TXDoptional, can be overridden
UART_DEV(2)RxDGPIO16UART2_RXDoptional, can be overridden
</center>

JTAG Interface {#esp32_jtag_interface_esp32c3}

There are two option on how to uese the JTAG interface on ESP32-C3:

  1. Using the built-in USB-to-JTAG bridge connected to an USB cable as follows:

    <center> USB Signal | ESP32-C3 Pin :--------------|:----------- D- (white) | GPIO18 D+ (green) | GPIO19 V_Bus (red) | 5V Ground (black) | GND </center>
  2. Using an external JTAG adapter connected to the JTAG interface exposed to GPIOs as follows:

    <center> JTAG Signal | ESP32-C3 Pin :-----------|:----------- TRST_N | CHIP_PU TDO | GPIO7 (MTDO) TDI | GPIO5 (MTDI) TCK | GPIO6 (MTCK) TMS | GPIO4 (MTMS) GND | GND </center>

    @note This option requires that the USB D- and USB D+ signals are connected to the ESP32-C3 USB interface at GPIO18 and GPIO19.

Using the built-in USB-to-JTAG is the default option, i.e. the JTAG interface of the ESP32-C3 is connected to the built-in USB-to-JTAG bridge. To use an external JTAG adapter, the JTAG interface of the ESP32-C3 has to be connected to the GPIOs as shown above. For this purpose eFuses have to be burned with the following command:

espefuse.py burn_efuse JTAG_SEL_ENABLE --port /dev/ttyUSB0

Once the eFuses are burned with this command and option JTAG_SEL_ENABLE, GPIO10 is used as a bootstrapping pin to choose between the two options. If GPIO10 is HIGH when ESP32-C3 is reset, the JTAG interface is connected to the built-in USB to JTAG bridge and the USB cable can be used for on-chip debugging. Otherwise, the JTAG interface is exposed to GPIO4 ... GPIO7 and an external JTAG adapter has to be used.

Alternatively, the integrated USB-to-JTAG bridge can be permanently disabled with the following command:

espefuse.py burn_efuse DIS_USB_JTAG --port /dev/ttyUSB0

Once the eFuses are burned with this command and option DIS_USB_JTAG, the JTAG interface is always exposed to GPIO4 ... GPIO7 and an external JTAG adapter has to be used.

@note Burning eFuses is an irreversible operation.

For more information about JTAG configuration for ESP32-C3, refer to the section [Configure Other JTAG Interface] (https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-guides/jtag-debugging/configure-other-jtag.html) in the ESP-IDF documentation.