src/ztex/fpga-descrypt/ztex_inouttraffic_summary.html
| ztex_inouttraffic Project Status (06/28/2017 - 11:38:33) | | Project File: | descrypt-ztex.xise | Parser Errors: | No Errors | | Module Name: | ztex_inouttraffic | Implementation State: | Programming File Generated | | Target Device: | xc6slx150-3csg484 |
| | | Product Version: | ISE 14.5 |
| | | Design Goal: | Balanced |
| All Signals Completely Routed | | Design Strategy: | descrypt |
| All Constraints Met | | Environment: | System Settings |
| 0 (Timing Report) |
| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers | 53,703 | 184,304 | 29% | |
| Number used as Flip Flops | 53,675 | | | |
| Number used as Latches | 28 | | | |
| Number used as Latch-thrus | 0 | | | |
| Number used as AND/OR logics | 0 | | | |
| Number of Slice LUTs | 53,817 | 92,152 | 58% | |
| Number used as logic | 44,476 | 92,152 | 48% | |
| Number using O6 output only | 36,628 | | | |
| Number using O5 output only | 156 | | | |
| Number using O5 and O6 | 7,692 | | | |
| Number used as ROM | 0 | | | |
| Number used as Memory | 2,220 | 21,680 | 10% | |
| Number used as Dual Port RAM | 744 | | | |
| Number using O6 output only | 40 | | | |
| Number using O5 output only | 0 | | | |
| Number using O5 and O6 | 704 | | | |
| Number used as Single Port RAM | 104 | | | |
| Number using O6 output only | 104 | | | |
| Number using O5 output only | 0 | | | |
| Number using O5 and O6 | 0 | | | |
| Number used as Shift Register | 1,372 | | | |
| Number using O6 output only | 27 | | | |
| Number using O5 output only | 0 | | | |
| Number using O5 and O6 | 1,345 | | | |
| Number used exclusively as route-thrus | 7,121 | | | |
| Number with same-slice register load | 7,111 | | | |
| Number with same-slice carry load | 10 | | | |
| Number with other load | 0 | | | |
| Number of occupied Slices | 15,823 | 23,038 | 68% | |
| Number of MUXCYs used | 1,684 | 46,076 | 3% | |
| Number of LUT Flip Flop pairs used | 58,562 | | | |
| Number with an unused Flip Flop | 17,921 | 58,562 | 30% | |
| Number with an unused LUT | 4,745 | 58,562 | 8% | |
| Number of fully used LUT-FF pairs | 35,896 | 58,562 | 61% | |
| Number of unique control sets | 566 | | | |
| Number of slice register sites lost
to control set restrictions | 2,244 | 184,304 | 1% | |
| Number of bonded IOBs | 44 | 338 | 13% | |
| Number of LOCed IOBs | 44 | 44 | 100% | |
| IOB Flip Flops | 62 | | | |
| Number of RAMB16BWERs | 134 | 268 | 50% | |
| Number of RAMB8BWERs | 6 | 536 | 1% | |
| Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% | |
| Number used as BUFIO2s | 1 | | | |
| Number used as BUFIO2_2CLKs | 0 | | | |
| Number of BUFIO2FB/BUFIO2FB_2CLKs | 1 | 32 | 3% | |
| Number used as BUFIO2FBs | 1 | | | |
| Number used as BUFIO2FB_2CLKs | 0 | | | |
| Number of BUFG/BUFGMUXs | 7 | 16 | 43% | |
| Number used as BUFGs | 5 | | | |
| Number used as BUFGMUX | 2 | | | |
| Number of DCM/DCM_CLKGENs | 3 | 12 | 25% | |
| Number used as DCMs | 1 | | | |
| Number used as DCM_CLKGENs | 2 | | | |
| Number of ILOGIC2/ISERDES2s | 20 | 586 | 3% | |
| Number used as ILOGIC2s | 20 | | | |
| Number used as ISERDES2s | 0 | | | |
| Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 586 | 0% | |
| Number of OLOGIC2/OSERDES2s | 22 | 586 | 3% | |
| Number used as OLOGIC2s | 22 | | | |
| Number used as OSERDES2s | 0 | | | |
| Number of BSCANs | 0 | 4 | 0% | |
| Number of BUFHs | 0 | 384 | 0% | |
| Number of BUFPLLs | 0 | 8 | 0% | |
| Number of BUFPLL_MCBs | 0 | 4 | 0% | |
| Number of DSP48A1s | 1 | 180 | 1% | |
| Number of ICAPs | 0 | 1 | 0% | |
| Number of MCBs | 0 | 4 | 0% | |
| Number of PCILOGICSEs | 0 | 2 | 0% | |
| Number of PLL_ADVs | 3 | 6 | 50% | |
| Number of LOCed PLL_ADVs | 3 | 3 | 100% | |
| Number of PMVs | 0 | 1 | 0% | |
| Number of STARTUPs | 1 | 1 | 100% | |
| Number of SUSPEND_SYNCs | 0 | 1 | 0% | |
| Average Fanout of Non-Clock Nets | 2.60 | | | |
| Performance Summary | [-] | | Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | | Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | | Timing Constraints: | All Constraints Met | | |
| Detailed Reports | [-] | | Report Name | Status | Generated | Errors | Warnings | Infos | | Synthesis Report | Current | 27. 23:23:55 2017 | 0 | 110 Warnings (110 new) | 32 Infos (32 new) | | Translation Report | Current | 28. 05:58:30 2017 | 0 | 2 Warnings (2 new) | 2 Infos (2 new) | | Map Report | Current | 28. 07:05:24 2017 | | | | | Place and Route Report | Current | 28. 08:29:31 2017 | 0 | 186 Warnings (186 new) | 1 Info (1 new) | | Power Report | | | | | | | Post-PAR Static Timing Report | Current | 28. 11:38:11 2017 | 0 | 2 Warnings (0 new) | 3 Infos (0 new) | | Bitgen Report | Current | 28. 09:02:31 2017 | 0 | 209 Warnings (209 new) | 1 Info (1 new) |
| Secondary Reports | [-] | | Report Name | Status | Generated | | WebTalk Log File | Current | 28. 09:03:13 2017 |
Date Generated: 06/28/2017 - 11:38:33