* - Term
  - Definition
* - **SPI**
  - Serial Peripheral Interface
* - **MSPI**
  - Memory SPI Peripheral, SPI Peripheral dedicated for memory
* - **SDR**
  - Single Data Transfer Rate (SDR), also known as STR (Single Transfer Rate)
* - **DDR**
  - Double Data Transfer Rate (DDR), also known as DTR (Double Transfer Rate)
* - **line mode**
  - Number of signals used to transfer data in the data phase of SPI transactions. e.g., for 4-bit-mode, the speed of the data phase would be 4 bit per clock cycle.
* - **FxRx**
  - F stands for flash, R stands for PSRAM, x stands for line mode. e.g., F4R4 stands for an {IDF_TARGET_NAME} with Quad flash and Quad PSRAM.

On {IDF_TARGET_NAME}, MSPI stands for the SPI0/1. SPI0 and SPI1 share a common SPI bus. The main flash and PSRAM are connected to the MSPI peripheral. CPU accesses them via Cache.

Configuration 1 of flash and PSRAM should be selected according to your actual hardware.

For the reset of the above configurations:

- Flash and PSRAM share the same internal clock.
- Quad flash only supports STR mode. Octal flash may support either/both STR/DTR modes under OPI mode, depending on the flash model and the vendor.
- Quad PSRAM only supports STR mode, while Octal PSRAM only supports DTR mode.

Therefore, some limitations should be noticed when configuring configuration 2, 3 and 4 of flash, and configuration 2 of PSRAM. Please refer to :ref:`All Supported Modes and Speeds <flash-psram-combination>`.

If a board with Octal flash resets before the second stage bootloader, please refer to :ref:`Error Handling Chapter <flash-psram-error>`.

For MSPI DDR mode, the data are sampled on both the positive edge and the negative edge. e.g., if a flash is set to 80 MHz and DDR mode, then the final speed of the flash is 160 MHz. This is faster than the flash setting to 120 Mhz and STR mode.

120 MHz DDR mode is an experimental feature. You will only see it when:

- :ref:`CONFIG_IDF_EXPERIMENTAL_FEATURES` is enabled

With above step, you will find 120 MHz option is visible.

Risks:

If your chip powers on at a certain temperature, then after the temperature increases or decreases over 20 celsius degree, the accesses to/from PSRAM/flash will crash randomly. Flash access crash will lead to program crash.

Note 20 celsius degree is not a totally correct number. This value may changes among chips.

The PSRAM requires a phase point calibration algorithm when operating at 120M. The phase point setting is related to the temperature at startup. When the temperature increases / decreases significantly during the operation of the chip, the PSRAM may experience read/write errors. To solve this problem, you can enable dynamic adjustment of the PSRAM phase point based on the temperature value with :ref:`CONFIG_SPIRAM_TIMING_TUNING_POINT_VIA_TEMPERATURE_SENSOR`. This creates a task that measures the temperature every :ref:`CONFIG_SPIRAM_TIMING_MEASURE_TEMPERATURE_INTERVAL_SECOND` seconds and adjusts the PSRAM phase point accordingly.

* - Group
  - Flash mode
  - Group
  - PSRAM mode
* - A
  - 120 MHz DDR
  - A
  - 120 MHz DDR
* - A
  - 120 MHz SDR
  - A
  -
* - B
  - 80 MHz DDR
  - B
  - 80 MHz DDR
* - C
  - 80 MHz SDR
  - C
  - 40 MHz DDR
* - C
  - 40 MHz DDR
  - C
  -
* - C
  - < 40 MHz
  - C
  -
* - D
  -
  - D
  - disable

* - Group
  - Flash mode
  - Group
  - PSRAM mode
* - A
  - 120 MHz SDR
  - A
  - 120 MHz DDR
* - B
  - 80 MHz SDR
  - B
  - 80 MHz DDR
* - C
  - 40 MHz SDR
  - C
  - 40 MHz DDR
* - C
  - 20 MHz SDR
  - C
  -
* - D
  -
  - D
  - disable

* - Group
  - Flash mode
  - Group
  - PSRAM mode
* - A
  - 120 MHz
  - A
  - 120 MHz
* - B
  - 80 MHz
  - B
  - 80 MHz
* - C
  - 40 MHz
  - C
  - 40 MHz
* - C
  - 20 MHz
  - C
  -
* - D
  -
  - D
  - disable

idf.py -p PORT efuse-burn --do-not-confirm FLASH_TYPE 1

This step is irreversible. Please do check if your hardware is actually using an Octal flash.