components/esp_hal_systimer/README.md
[!NOTE] This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
The ESP Hardware Abstraction Layer for System Timer Peripheral (esp_hal_systimer) provides a unified interface to interact with the system timer (SYSTIMER) peripheral across all ESP chip families. This component abstracts the hardware-specific details of different SYSTIMER implementations, enabling consistent usage patterns regardless of the underlying hardware.
The SYSTIMER is a high-resolution timer used for:
The HAL architecture consists of two primary layers:
HAL Layer (Upper): Defines the operational sequences and data structures required to interact with the SYSTIMER peripheral, including:
Low-Level Layer (Bottom): Acts as a translation layer between the HAL and the register definitions in the soc component, handling:
This component is primarily used by ESP-IDF system services such as:
For advanced developers implementing custom timing solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
soc: Provides chip-specific register definitionshal: Core hardware abstraction utilities and macrosesp_rom: ROM function interfaces (when using ROM implementation)Some chips support using ROM-based SYSTIMER HAL implementations for reduced code size. This is controlled by the CONFIG_HAL_SYSTIMER_USE_ROM_IMPL configuration option. When enabled, the component uses ROM linker scripts to link against ROM functions instead of compiling the HAL implementation.