components/esp_hal_clock/README.md
[!NOTE] This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
The esp_hal_clock component provides the Hardware Abstraction Layer for the SoC clock tree across ESP-IDF supported targets. It exposes helpers to query and configure clock sources, select roots, and manage clock gates in a target-agnostic way while delegating register details to per-target Low-Level (LL) implementations.
The Clock HAL is organized in two layers:
clk_tree_ll.h — clock source/root select, muxes, dividers, and frequency helpers.clk_gate_ll.h — clock gate enable/disable, reset, and configuration of default clock gate status for peripherals.clkout_channel.h — clock output channel IDs and related helpers used to route internal clocks to GPIOs.Per-target HAL sources implement SoC-specific behavior in clk_tree_hal.c, using the LL accessors above.
clkout_channel.h) on supported targets.This HAL is consumed by ESP-IDF internal components (e.g., esp_hw_support, drivers, bootloader code) to perform clock configuration and queries.
Advanced users may interact with the HAL directly when implementing custom bring-up or performance-sensitive flows. API stability is not guaranteed during beta.
soc: SoC register definitions and clock tree constantshal: Common HAL utilities and macros