packages/chip/research/ai_accelerator_sota/00_index.md
Date: 2026-05-19
This packet records a source-backed survey of TPU, GPU, mobile NPU, open accelerator, and sub-2 nm process literature relevant to the Eliza E1 AI SoC scaffold.
01_sources/source_inventory.yaml: provenance, local downloads, and claim
boundaries.02_analysis/sota_synthesis.md: architecture findings and competitive
lessons.02_analysis/open_source_cores.md: reusable open-source GPU/NPU/TPU
implementation references.02_analysis/process_14a_sub2nm_notes.md: 14A, backside power, nanosheet,
packaging, thermal, and reliability implications.03_implementation/e1_ai_optimization_plan.md: ranked features and
verification gates for integration into E1.This is a research and implementation-planning artifact, not taped-out evidence. Public vendor claims are treated as targets or directional guidance until reproduced through local models, RTL, synthesis, physical design, or board evidence.