Intel 14A stub — strategic 2nd source 2028 (BLOCKED)

Fail-closed evidence file for Intel 14A. Intel 14A is the project's strategic 2nd source: 2nd-gen PowerVia BSPDN plus industry-first commercial High-NA EUV. 14A is only realistic for non-Apple customers, possibly through a DARPA / RAMP-C or hyperscaler diversification path.

No 14A PDK data, library, GDS, LEF, extraction view, SRAM macro, PHY hard-IP, or signoff report is or will be checked in until an IFS agreement is in place.

BSPDN brings real methodology cost: thermal-coupling uplift through thinned silicon, two-sided power-grid extraction, new probe / test access, multi-quarter bring-up learning curve. High-NA brings new litho / DFM constraints and a scanner-allocation gate from ASML.

Related:

• pd/corner-manifests/intel-14a.yaml
• pd/library-manifests/intel-14a.yaml
• docs/pd/process-node-selection.md
• docs/evidence/process/pdk-access-gate.yaml