Power Delivery SOTA — 2028 RISC-V Phone-Class AP

Sub-report of 2028-sota-integrated-report.md.

A. SOTA snapshot — mobile-class SoC PDN

A.1 PMIC / external regulator landscape

A.2 On-die regulator and droop sensor practice

• Intel FIVR (4th-gen Core, 22 nm, 2013) — 140 MHz multi-phase buck with package-trace inductors; on-die MIM caps. 80 MHz unity-gain BW.
• Intel MIA + FIVR2 (10th-gen, 2020) — magnetic inductor array on-package.
• Distributed digital LDOs — 28 nm distributed dLDOs published with ~100 mV droop / 500 mA load / settling <20 ns. Newer 22 nm computational dLDOs target 10 A class for big cores with sub-20-ns transient.
• Adaptive clocking for droop tolerance — IBM POWER9 and AMD 28 nm x86-64 publish full ACS systems: clock stretches on droop detection within 1-3 cycles, recovers within tens of cycles.
• Apple specifics largely undocumented in primary literature, but iPhone-class chips widely understood (via patents and teardown) to use per-cluster LDOs and adaptive clocking — Apple holds multiple droop-detector / supply-droop-compensation patents (USPTO 10145868, 10320375, 10749513, 11397444).

A.3 Backside power delivery (BSPDN / PowerVia / SPR)

• Intel PowerVia (production, 18A in 2025) — first production BSPDN. Internal E-core test vehicle with > 90% utilization shows: >30% platform voltage droop improvement, 6% frequency benefit at iso-voltage, looser frontside metal pitch reducing lithography cost.
• TSMC A14 (production 2028) — first version is frontside-PDN only for mobile/client. Separate A14 + SPR (Super Power Rail) = informally "A12" with BSPDN ships in 2029.
• Samsung SF2 has BSPDN roadmap; Exynos 2600 reported on SF2 without BSPDN.
• Thermal trade-off: BSPDN puts power TSVs through bulk, removing thermal contact between active devices and substrate top side. SemiEngineering and IRDS 2024 flag higher local Tj because heat travels through BEOL of carrier rather than directly out back. Cooling at package and board must compensate.

A.4 On-die decap density

• TSMC SHPMIM caps for N2: > 2× density vs SHDMIM, 50% lower sheet/via resistance.
• TSMC iCAP (CoWoS interposer DTC) — 340 nF/mm².
• Mobile-class on-die decap rule-of-thumb (teardown analysis): ~5-10× total Cdecap-to-Cload in package + die combined, with deep-trench MIM contributing the majority of high-frequency response (1-100 MHz); package + board caps cover 10 kHz-10 MHz.

A.5 Mobile SoC power envelope (public + measured)

B. Current state in packages/chip

Gap: design-document level only on PDN; ~830× scaling distance between OpenLane demo current (3 mA on VDDCORE) and 2028 phone-class draw (~5 A across all core rails at ~0.7 V).

C. Recommended 2028 target

C.1 Process anchor

• Primary release: TSMC A14 (frontside PDN), HVM 2028, 2nd-gen GAA nanosheet.
• Stretch/follow-on: A14 + SPR ("A12") BSPDN variant, HVM 2029 — opt-in DTCO swap (separate pd/openroad/ config), not critical path. Budget shows +6% perf and 30% droop reduction if thermal mitigation closes.
• Backup: Samsung SF2P (BSPDN) — second-source.

C.2 Rail topology — 16 rails (production 2028 SKU)

Aligned with soc-optimized-operating-point.yaml's 2-core CPU + NPU + memory layout, scaled to phone-class. Budget targets, not measurements.

Sum: ~5.0 W peak, ~3.5 W sustained at 95 °C Tj, ~1.0 W idle. Matches soc-optimized-operating-point.yaml (max 4.57 W modeled).

C.3 On-die regulator strategy

• Per-core dLDO on big-CPU and NPU. Target <20 ns droop response, ~5% drop @ full step.
• No FIVR-class buck on-die in v0 — area cost too high for first open mobile SoC. Switched-capacitor 2:1 SC-DC in v1 if pd/openlane supports cap density.
• AON retention LDO in always-on island to hold mgmt-core state during deep sleep (S3-equivalent).

C.4 Adaptive clocking + droop sensing

• Droop sensor per voltage domain — ring-oscillator-based, <1 ns droop detect, sampled at 200 MHz. Reference: 22 nm all-digital ADCD (Bowman/Tokunaga).
• Clock stretcher per CPU/NPU core, 1-cycle response. Implementation: programmable phase-blender.
• AVFS loop — closed-loop voltage tuning driven by in-situ timing margin monitors (canary FFs); 100 µs update; 6.25 mV voltage delta.

C.5 Decap budget

• On-die: SHPMIM-class (A14 equivalent) deep-MIM, target 150 nF/mm² average. Hot-rail CPU/NPU islands target 5× ICs/Iavg ratio = ~250 nF on 12 mm² die area-stretch.
• Package: 0.1-10 µF cap bank between BGA balls, ≥40 caps for 5 W SoC.
• Board: bulk 22-100 µF tantalum/MLCC near each external buck; ≥4 high-frequency 100 nF MLCCs per ball pair on each core rail.

C.6 Power-management firmware stack

S-mode Linux  --SBI MPXY (sysbus mailbox)-->  M-mode OpenSBI
                                                  |
                                                  | RPMI v1.0
                                                  v
                                          Eliza Power-Mgmt Core (Ibex-32)
                                                  |
                                                  |  SPMI / I2C / RPMSG-equivalent
                                                  v
                                              External PMIC set

• RISC-V MPXY SBI extension (ratified SBI v3.0) + RPMI v1.0 (ratified) — drop-in equivalent to Arm SCMI; reuse Linux clk/regulator/cpufreq infrastructure with SBI MPXY mailbox drivers (merged for 6.x).
• Power-mgmt core: Ibex-class RV32IMC, gated on AON, runs always-on. Owns: PMIC sequencing, DVFS table arbitration, thermal throttle policy, droop telemetry, secure-boot keys.
• DVFS tables: per-corner (SS/TT/FF + 0/25/85/105 °C), generated at characterization from pd/signoff/sta/*.

D. Benchmarks / evaluation / testing

D.1 Pre-silicon

1. Activity-traced power signoff — real workload VCDs (Geekbench-equivalent int trace, MLPerf Mobile NPU INT8, LLM-7B-INT4 token loop, sustained NPU CNN, idle, display refresh) through PrimePower (commercial) or OpenSTA + Capacitate (open) into pd/signoff/power.rpt. Replaces modeled numbers in soc-optimized-operating-point.yaml.
2. Static IR-drop signoff — Voltus or RedHawk-SC at SS/TT/FF + 4 thermal corners, all 16 rails. Acceptance: <5% nominal Vdd droop.
3. Dynamic IR-drop signoff — vector-driven dynamic with worst-case vectors per block (CPU integer burst, NPU GEMM saturation, CPU+NPU+display simultaneous). Acceptance: <10% droop, AVFS-corrected timing must close.
4. EM signoff — foundry-mandated current density limits on all PG layers + clock/reset signal wires. Lifetime derate ≥10 years at 85 °C avg Tj.
5. PDN impedance — Z_pdn(f) under 5 mΩ DC and <15 mΩ across 1 kHz-1 GHz. Resonance peaks tracked at package + board boundary.
6. Anti-resonance + Ldi/dt — simulate worst slew (CPU NEON-equivalent saturation → idle in 1 cycle) with package + board model.

D.2 Post-silicon

1. Power-virus workload — synthesize custom RTL "current bomb" (mprime + stressapptest + INT8-GEMM saturation analog) calibrated to peak modeled rail current.
2. Sustained perf-vs-temp — 30-min runs at 25 °C ambient → measure Tj, throttle response, sustained Geekbench, MLPerf, LLM tok/s. Compare to:
   • A19 Pro sustained Geekbench multi (~8500 after ~10 min)
   • Snapdragon 8 Elite Gen 5 sustained Geekbench multi (~9200)
   • Dimensity 9500 sustained Geekbench multi (~8400)
3. DVFS table tuning per silicon corner — characterize each chip at SS/TT/FF and bin into 3 voltage tables.
4. Droop event capture — on-die telemetry of droop sensor events during workload transitions; expect <1 event/sec at production V/F.
5. Skin-temperature correlation — chamber + free-air with phone-class enclosure; cross-reference benchmarks/power/manifests/e1-npu-sustained-capture.template.json.

E. Optimizations: has / should / needs

Has

• Two-rail demo padframe with explicit IO/core separation.
• Operating-point optimizer with corner sweep (make soc-optimization).
• Process effects contract distinguishing FSPDN and BSPDN variants (docs/spec-db/process-14a-effects.yaml).
• Local IR-drop reporting from OpenROAD on Sky130 demo.

Should (P1, 2028 target)

• Per-domain power gating with retention FFs on caches/regfiles. UPF (IEEE 1801) for every island.
• Per-cluster fast DVFS via on-die dLDOs (CPU big, NPU).
• AVFS loop + droop sensors + clock stretchers.
• Thermal-aware DVFS with on-die DTSs (≥8 sensors, one per power island).
• SBI MPXY + RPMI power-management firmware on Ibex management core.
• DTC + MIM on-die decap sized 5× Cload, per-rail allocation.

Definitely needs (P0, gates the chip)

• Pick a PMIC vendor or design discrete bucks/LDOs. Open mobile-class PMIC IP does not exist publicly. Options:
  1. Buy Renesas/MPS/TI/Maxim mobile PMIC catalog parts and use 4-6 in parallel.
  2. License closed IP (Synaptics, Dialog) — slow, expensive.
  3. Custom analog design — requires analog team and separate older-node tapeout (realistic for v0: discrete PMIC daughtercard from 8-12 catalog regulators, hop to integrated for v1).
• Authoritative rail list and UPF. Today's 2-rail padframe good only for Sky130 demo. 14A SKU must publish 16-rail map and freeze before RTL closes.
• Power signoff EDA path. OpenROAD static IR-drop is triage. Buy Voltus or RedHawk-SC seats; gap to open EDA in dynamic IR/EM is years.
• Activity-traced power — replace OpenLane metrics.json mW with VCD-driven power.rpt for: NPU INT8 GEMM saturation, CPU integer burst, idle, display refresh.
• Package model with bond-wire / BGA inductance in PDN sim. Pad-frame R/L from pd/openlane/runs/.../padframe_inclusive_lvs must feed back into IR-drop.

F. Risks and open questions

Concrete next moves (≤ 4 weeks)

1. Author docs/pd/rail-plan-2028.yaml listing 16 rails, nominal V, DVFS range, peak/avg I, regulator type, decoupling target. Bind to pd/signoff/manifest.yaml.
2. Add docs/pd/pmic-selection.md with 3 candidate paths (catalog-daughtercard / closed-IP / custom analog); pick v0 path.
3. UPF skeleton in pd/upf/e1_soc_top.upf: 16 power domains, isolation cells, retention per island. UPF gate added to make pd-check.
4. Stand up rtl/power/droop_sensor.sv + rtl/power/clock_stretcher.sv ports of public 22 nm designs; cocotb tests for droop event injection.
5. scripts/check_pdn_workload_signoff.py — fails closed if pd/signoff/<RUN>/reports/ir_drop.rpt is not vector-driven, multi-corner, signed by Voltus/RedHawk OR explicitly waived with open-flow fallback margin.
6. Wire soc-optimized-operating-point.yaml to rail-plan; gate operating-point report on rail-plan hash, so future modeled-power changes invalidate the claim.
7. RFC: choose SBI MPxy + RPMI as power-management ABI. Open issue against docs/project/spec-rtl-sw-pd-handoff-work-order.yaml.

Sources

• Qualcomm Snapdragon 8 Elite Gen 5 brief
• Qualcomm RPMh
• Linux qcom,rpmh-regulator DT binding
• Linaro: Qualcomm PM8550 mainline
• MediaTek Dimensity 9500
• LKML — MediaTek MT6373 PMIC binding (Oct 2025)
• Intel PowerVia IEEE VLSI 2023
• Semiconductor Engineering: BSPDN thermal challenges
• TSMC A14 2028 production, BSPDN slips to 2029
• Intel FIVR — IEEE ISSCC 2013
• Intel MIA — IEEE 2020
• Computational digital LDO for mobile SoC big-core (2024)
• POWER9 adaptive clocking ISSCC
• 22 nm all-digital ADCD — Bowman/Tokunaga
• Apple droop-detector patents: USPTO 10145868, 10320375, 10749513, 11397444
• TSMC SHPMIM N2 capacitor
• Deep-trench capacitor — WikiChip
• Real World Tech — Power delivery in a modern processor
• Ansys RedHawk-SC
• Synopsys VC LP — UPF static signoff
• IEEE 1801 / UPF 4.0 — DVCon 2024
• OpenSBI — RISC-V MPXY + RPMI v1.0
• LWN — Linux SBI MPXY and RPMI
• SBI MPXY mailbox DT binding RFC v2
• Notebookcheck Snapdragon 8 Elite Gen 5
• Notebookcheck Apple A19 Pro
• Notebookcheck Dimensity 9500
• Samsung Exynos 2600