SoC integration contract

e1_soc_integrated is the top-level SystemVerilog integration of the eight domain agent deliverables. It is not a replacement for the v0 e1_chip_top + e1_soc_top path used by the existing release flow; it is a parallel top that demonstrates the cross-domain interfaces wire up at the SystemVerilog level and is gated by a fail-closed evidence manifest.

Domain instantiation map

Cross-domain interfaces

Every edge between two domains must be wired exactly once; this top is the canonical location for the wiring.

BPU → Zihpm (PMU events)

bpu_top.pmu_strb[19:0]  →  bpu_to_zihpm_remap.bpu_strobes_i
                            │
                            └→  zihpm.event_bus_i[255:0]
                                 ↓
                                 mhpmcounter[3..15] increment per
                                 mhpmevent selector

Width contract: BPU emits 20 PMU strobes (PMU_BR_PRED..PMU_SC_OVERRIDE, 5-bit IDs); the remap shifts them by +1 (to leave EVT_NONE=0) and renames PMU_FTB_MISS → EVT_BTB_MISS. See scripts/check_pmu_event_alignment.py for the strict harmonization checker. Verified by verify/cocotb/integration/test_cross_domain_interfaces.py::bpu_pmu_strobe_increments_zihpm_counter.

BPU → L1I (FTQ prefetch)

bpu_top.fetch_entry        →  ftq_to_l1i_shim.fetch_entry
bpu_top.fetch_valid        →  ftq_to_l1i_shim.fetch_entry_valid
resolve_i.misprediction    →  ftq_to_l1i_shim.flush_valid
                                ↓
                                ftq_prefetch_req_t {paddr_line[39:0],
                                                    confidence[2:0],
                                                    branch_target}
                                exposed on SoC port l1i_prefetch_req_o

Width contract: 39-bit Sv39 virtual PC drops the bottom 6 bits and zero-extends to a 40-bit physical line address. Confidence is {0,4,5,6} for {BR_NONE, BR_COND, BR_CALL, BR_RET}. See rtl/cache/ftq_to_l1i_pkg.sv for the canonical packet shape. Verified by ftq_l1i_shim_emits_prefetch_on_taken_target and ftq_l1i_shim_flushes_on_misprediction.

CPU cluster → AXI4 fabric

The cluster presents 8 per-core AXI4 master ports (1 big + 3 mid + 4 little) with AXI_ADDR_W=40, AXI_DATA_W=128, AXI_ID_W=8. The integrated top currently routes only the cache-side CHI → AXI4 bridge into the fabric (master 0); the per-core cluster ports stay tied off in e1_cluster_top lite mode until the core wrappers ship. This is the documented BLOCKED edge — see docs/evidence/integration/cross-domain-interfaces.yaml.

CHI → AXI4 (cache south boundary)

e1_slc / SLC banks  →  TL-C  →  tl_c_to_chi_bridge  →  CHI  →
   e1_chi_to_axi4_bridge  →  fabric master[0]  →  DRAM

The e1_chi_to_axi4_bridge issues 6-bit IDs; the fabric runs 4-bit IDs for the rest of the masters. An adapter at the boundary slices the low 4 bits and pads the high 2 bits to zero on the way back. See rtl/top/adapters/README.md for the documented width drift.

IOMMU translation (non-coherent masters)

NPU / DMA / display masters  →  e1_riscv_iommu.u_*  →  AXI4 d_*
                                                    →  fabric master[1]
                                                    →  DRAM

The IOMMU surfaces fault_irq, page_req_irq, and cmd_complete_irq. The integration top exposes fault_irq + fault_count at the SoC boundary. The CPU is coherent and does not route through the IOMMU; it uses the CHI bridge directly.

PMC mailbox (AON ↔ main rail)

mmio_addr[31:16] == 0x1005_xxxx     →  pmc_top.mbox_*
                                       ↓
                                       reg_tx_*, reg_rx_*, reg_dvfs_*
                                       ↓
                                       wake_irq_o, thermal_irq_o,
                                       dvfs_request_*, droop telemetry

The PMC AON Ibex consumes telemetry and writes DVFS requests; the mailbox surface is documented in rtl/power/power_pkg.sv. Note that the PMC mailbox read path is registered (rdata_q), so a CPU read takes one extra cycle compared to the combinational v0 peripherals.

Address map

The 40-bit fabric DRAM lives behind e1_axi4_interconnect and is addressed separately from the v0 32-bit MMIO aperture above. The two share no addresses: the fabric DRAM is the south side of the cache hierarchy; the v0 DRAM aperture is what the legacy DMA / NPU / display masters drive.

Documented adapter drift

What this top does NOT prove

These items remain BLOCKED until later work; the integration top is explicit about them:

• Real CPU execution (no core wrappers in lite mode).
• Real coherent MESI traffic (cache RTL not instantiated; covered in verify/cocotb/cache/).
• Real DFI 5.0 PHY (BLOCKED under docs/evidence/memory/lpddr-phy-procurement.yaml).
• IPC / GB6 / MLPerf numbers — BLOCKED until silicon.

Evidence