Design Rule Verification Report

| Date: | | һ 03-14 | | Time: | | 10:36:46 | | Elapsed Time: | | 00:00:02 | | Filename: | | E:\OnWorking\ElectronBot\1.Hardware\SensorBoard\SensorBoard.PcbDoc |

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| Warnings: | | 0 | | Rule Violations: | | 0 |

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Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=4mil) (All),(All)	0
Clearance Constraint (Gap=8mil) (InNetClass('Logo')),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=4mil) (Max=10000mil) (Preferred=4mil) (All)	0
Width Constraint (Min=4mil) (Max=50mil) (Preferred=10mil) ((InNet('VDD_SYS_3.3V') OR InNet('VDD_AV_3.3V') OR InNet('VDD_5V') OR InNet('VDD1V2-SYS') OR InNet('VDD1V1-EPHY') OR InNet('VDD-CPUX') OR InNet('VDD-CPUS') OR InNet('VDD-CPUFB') OR InNet('VCC-DRAM')))	0
Width Constraint (Min=0.1mil) (Max=100mil) (Preferred=10mil) (InNetClass('Logo'))	0
Width Constraint (Min=4mil) (Max=50mil) (Preferred=10mil) ((InNet('AGND') OR InNet('GND')))	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=8mil) (Max=10000mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=2mil) (Disabled)(All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0