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Functionality

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Functionality

Note : CUTLASS-3 requires users to use CUDA 11.4 or newer, and SM70 or newer, for the target toolkit and architecture, respectively.

  • N - Column Major Matrix
  • T - Row Major matrix
  • {N,T} x {N,T} - All combinations, i.e., NN, NT, TN, TT
  • NHWC - 4 dimension tensor used for convolution
  • NCxHWx - Interleaved 4 dimension tensor used for convolution
  • f - floating point
  • s - signed int
  • b - bit
  • cf - complex float
  • bf16 - bfloat16
  • tf32 - tfloat32
  • Simt - Use Simt CUDA Core MMA
  • TensorOp - Use Tensor Core MMA
  • SpTensorOp - Use Sparse Tensor Core MMA
  • WmmaTensorOp - Use WMMA abstraction to use Tensor Core MMA

Device-level GEMM

The following tables summarize device-level GEMM kernels in CUTLASS, organized by opcode class, data type, and layout. Hyperlinks to relevant unit tests demonstrate how specific template instances may be defined.

CUTLASS 3.x Kernels

Opcode ClassCompute CapabilityCUDA ToolkitData TypeLayoutsUnit Test
TensorOp90a12.0+f16 * f16 + { f16, f32 } => { f16, f32 }{N,T} x {N,T} => {N,T}example
TensorOp90a12.0+bf16 * bf16 + { f16, f32 } => { bf16, f32 }{N,T} x {N,T} => {N,T}example
TensorOp90a12.0+{f32, tf32} * {f32, tf32} + f32 => f32{ T } x { N } => {N,T}example
TensorOp90a12.0+s8 * s8 + s32 => {s32, s8}{ T } x { N } => {N,T}example

CUTLASS 2.x Kernels

Opcode ClassCompute CapabilityCUDA ToolkitData TypeLayoutsUnit Test
Simt50+11.4+f32 * f32 + f32 => f32{N,T} x {N,T} => {N,T}example
Simt50+11.4+f64 * f64 + f64 => f64{N,T} x {N,T} => {N,T}example
Simt60+11.4+f16 * f16 + f16 => f16{N,T} x {N,T} => {N,T}example
Simt61+11.4+s8 * s8 + s32 => {s32,s8}{N,T} x {N,T} => {N,T}example
WmmaTensorOp70+11.4+f16 * f16 + f16 => f16{N,T} x {N,T} => {N,T}example
WmmaTensorOp70+11.4+f16 * f16 + f32 => {f16, f32}{N,T} x {N,T} => {N,T}example
WmmaTensorOp75+11.4+s8 * s8 + s32 => {s32, s8}{N,T} x {N,T} => {N,T}example
WmmaTensorOp75+11.4+s4 * s4 + s32 => {s32, s4}{N,T} x {N,T} => {N,T}example
WmmaTensorOp75+11.4+b1 ^ b1 + s32 => {s32, b1}{ T } x { N } => {N,T}example
TensorOp70+11.4+f16 * f16 + f16 => f16{N,T} x {N,T} => {N,T}example
TensorOp70+11.4+f16 * f16 + f32 => {f16, f32}{N,T} x {N,T} => {N,T}example
TensorOp75+11.4+f16 * f16 + f16 => f16{N,T} x {N,T} => {N,T}example
TensorOp75+11.4+f16 * f16 + f32 => {f16, f32}{N,T} x {N,T} => {N,T}example
TensorOp75+11.4+s8 * s8 + s32 => {s32, s8}{ T } x { N } => {N,T}example
TensorOp75+11.4+s4 * s4 + s32 => {s32, s4}{ T } x { N } => {N,T}example
TensorOp75+11.4+b1 ^ b1 + s32 => {s32, b1}{ T } x { N } => {N,T}example
TensorOp80+11.4+f16 * f16 + f16 => f16{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+f16 * f16 + f32 => {f16, f32}{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+bf16 * bf16 + f32 => {bf16, f32}{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+tf32 * tf32 + f32 => f32{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+s8 * s8 + s32 => {s32, s8}{ T } x { N } => {N,T}example
TensorOp80+11.4+s4 * s4 + s32 => {s32, s4}{ T } x { N } => {N,T}example
TensorOp80+11.4+b1 ^ b1 + s32 => {s32, b1}{ T } x { N } => {N,T}example
TensorOp80+11.4+f64 * f64 + f64 => f64{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+cf32 * cf32 + cf32 => cf32{N,T} x {N,T} => {N,T}example
TensorOp80+11.4+cf64 * cf64 + cf64 => cf64{N,T} x {N,T} => {N,T}example, Gaussian 3m
SpTensorOp80+11.4+f16 * f16 + f32 => {f16, f32}{N,T} x {N,T} => {N,T}example
SpTensorOp80+11.4+bf16 * bf16 + f32 => {bf16, f32}{N,T} x {N,T} => {N,T}example
SpTensorOp80+11.4+tf32 * tf32 + f32 => f32{N,T} x {N,T} => {N,T}example
SpTensorOp80+11.4+s8 * s8 + s32 => {s8, s32}{N,T} x {N,T} => {N,T}example
SpTensorOp80+11.4+s4 * s4 + s32 => {s4, s32}{N,T} x {N,T} => {N,T}example
TensorOp90+11.8+f64 * f64 + f64 => f64{N,T} x {N,T} => {N,T}example

Device-level Implicit GEMM convolution

The following table summarizes device-level implicit GEMM convolution kernels in CUTLASS, organized by opcode class, data type, and layout. Hyperlinks to relevant conv2d fprop unit tests demonstrate how specific template instances may be defined. One can find and/or create equivalent dgrad and wgrad convolutional operators.

Opcode ClassCompute CapabilityCUDA ToolkitData TypeLayoutsUnit Test
Simt50+11.4+f32 * f32 + f32 => f32NHWCexample
Simt50+11.4+cf32 * cf32 + cf32 => cf32NHWCexample
TensorOp70+11.4+f16 * f16 + f32 => {f16, f32}NHWCexample
TensorOp75+11.4+f16 * f16 + f32 => {f16, f32}NHWCexample
TensorOp75+11.4+s8 * s8 + s32 => {s32, s8}NHWC, NCxHWxexample, ncxhwx
TensorOp75+11.4+s4 * s4 + s32 => {s32, s4}NHWC, NCxHWxexample, ncxhwx
Simt80+11.4+f32 * f32 + f32 => f32NHWCexample
Simt80+11.4+cf32 * cf32 + cf32 => cf32NHWCexample
TensorOp80+11.4+f16 * f16 + f32 => {f16, f32}NHWCexample
TensorOp80+11.4+f16 * f16 + f16 => f16NHWCexample
TensorOp80+11.4+tf32 * tf32 + f32 => f32NHWCexample
TensorOp80+11.4+s8 * s8 + s32 => {s32, s8}NHWC, NCxHWxexample, ncxhwx
TensorOp80+11.4+s4 * s4 + s32 => {s32, s4}NHWC, NCxHWxexample, ncxhwx

Warp-level Matrix Multiply with Tensor Cores

The following table summarizes supported warp level shapes for each TensorOp instruction.

Opcode ClassInstruction ShapeWarp Shapes
TensorOp8-by-8-by-432x32x4, 32x64x4, 64x32x4, 64x64x4
TensorOp16-by-8-by-832x32x8, 32x64x8, 64x32x8, 64x64x8
TensorOp16-by-8-by-1632x32x16, 32x64x16, 64x32x16, 64x64x16
TensorOp8-by-8-by-1632x32x16, 32x64x16, 64x32x16, 64x64x16
TensorOp8-by-8-by-3232x32x32, 32x64x32, 64x32x32, 64x64x32
TensorOp16-by-8-by-3232x32x32, 32x64x32, 64x32x32, 64x64x32
TensorOp16-by-8-by-6432x32x64, 32x64x64, 64x32x64, 64x64x64
TensorOp8-by-8-by-12832x32x128, 32x64x128, 64x32x128, 64x64x128
TensorOp16-by-8-by-25632x32x256, 32x64x256, 64x32x256, 64x64x256
SpTensorOp16-by-8-by-1664x64x16, 64x32x16, 32x64x16, 32x32x16
SpTensorOp16-by-8-by-3264x64x32, 64x32x32, 32x64x32, 32x32x32
SpTensorOp16-by-8-by-6464x64x64, 64x32x64, 32x64x64, 32x32x64
SpTensorOp16-by-8-by-12864x64x128, 64x32x128, 32x64x128, 32x32x128

TensorOp instructions depend on a permuted shared memory layout that can be efficiently loaded from. The following tables summarize the destination shared memory layout that can be targeted by matrix operands. It is assumed that each thread loads 128b vectors from global memory with layout specified in the column "GMEM Layout."

TensorOp 8-by-8-by-4.

OperandElementGMEM LayoutSMEM Layout
Ahalf_tColumnMajorColumnMajorVoltaTensorOpCongruous<16>
Ahalf_tRowMajorRowMajorVoltaTensorOpCrosswise<16>
Bhalf_tColumnMajorColumnMajorVoltaTensorOpCrosswise<16>
Bhalf_tRowMajorRowMajorVoltaTensorOpCongruous<16>
Chalf_tRowMajorRowMajor
CfloatRowMajorRowMajor

TensorOp 16-by-8-by-8.

OperandElementGMEM LayoutSMEM Layout
Ahalf_tColumnMajorColumnMajorTensorOpCongruous<16>
Ahalf_tRowMajorRowMajorTensorOpCrosswise<16>
Bhalf_tColumnMajorColumnMajorTensorOpCrosswise<16>
Bhalf_tRowMajorRowMajorTensorOpCongruous<16>
Chalf_tRowMajorRowMajor
CfloatRowMajorRowMajor

TensorOp 16-by-8-by-8.

OperandElementGMEM LayoutSMEM Layout
Atfloat32_tColumnMajorColumnMajorTensorOpCongruous<32>
Atfloat32_tRowMajorRowMajorTensorOpCrosswise<32>
Btfloat32_tColumnMajorColumnMajorTensorOpCrosswise<32>
Btfloat32_tRowMajorRowMajorTensorOpCongruous<32>
CfloatRowMajorRowMajor

TensorOp 16-by-8-by-16.

OperandElementGMEM LayoutSMEM Layout
Ahalf_t, bfloat16_tColumnMajorColumnMajorTensorOpCongruous<16>
Ahalf_t, bfloat16_tRowMajorRowMajorTensorOpCrosswise<16>
Bhalf_t, bfloat16_tColumnMajorColumnMajorTensorOpCrosswise<16>
Bhalf_t, bfloat16_tRowMajorRowMajorTensorOpCongruous<16>
Chalf_tRowMajorRowMajor
CfloatRowMajorRowMajor

TensorOp 8-by-8-by-4.

OperandElementGMEM LayoutSMEM Layout
AdoubleColumnMajorColumnMajorTensorOpCongruous<64>
AdoubleRowMajorRowMajorTensorOpCrosswise<64>
BdoubleColumnMajorColumnMajorTensorOpCrosswise<64>
BdoubleRowMajorRowMajorTensorOpCongruous<64>
CdoubleRowMajorRowMajor

TensorOp 8-by-8-by-16.

OperandElementGMEM LayoutSMEM Layout
Aint8_tRowMajorRowMajorTensorOpCrosswise<8>
Bint8_tColumnMajorColumnMajorTensorOpCongruous<8>
Cint32_tRowMajorRowMajor

TensorOp 16-by-8-by-32.

OperandElementGMEM LayoutSMEM Layout
Aint8_tRowMajorRowMajorTensorOpCrosswise<8>
Bint8_tColumnMajorColumnMajorTensorOpCongruous<8>
Cint32_tRowMajorRowMajor

TensorOp 8-by-8-by-32.

OperandElementGMEM LayoutSMEM Layout
Aint4b_tRowMajorRowMajorTensorOpCrosswise<4>
Bint4b_tColumnMajorColumnMajorTensorOpCongruous<4>
Cint32_tRowMajorRowMajor

TensorOp 16-by-8-by-64.

OperandElementGMEM LayoutSMEM Layout
Aint4b_tRowMajorRowMajorTensorOpCrosswise<4>
Bint4b_tColumnMajorColumnMajorTensorOpCongruous<4>
Cint32_tRowMajorRowMajor

TensorOp 8-by-8-by-128.

OperandElementGMEM LayoutSMEM Layout
Abin1_tRowMajorRowMajorTensorOpCrosswise<4>
Bbin1_tColumnMajorColumnMajorTensorOpCongruous<4>
Cint32_tRowMajorRowMajor

SpTensorOp 16-by-8-by-16.

OperandElementGMEM LayoutSMEM Layout
Atfloat32_tRowMajorRowMajorTensorOpCrosswise<32, 32>
Btfloat32_tColumnMajorColumnMajorTensorOpCrosswise<32, 32>
CfloatRowMajorRowMajor

SpTensorOp 16-by-8-by-32.

OperandElementGMEM LayoutSMEM Layout
Ahalf_tRowMajorRowMajorTensorOpCrosswise<16, 64>
Bhalf_tColumnMajorColumnMajorTensorOpCrosswise<16, 64>
CfloatRowMajorRowMajor

SpTensorOp 16-by-8-by-64.

OperandElementGMEM LayoutSMEM Layout
Aint8_tRowMajorRowMajorTensorOpCrosswise<8, 128>
Bint8_tColumnMajorColumnMajorTensorOpCrosswise<8, 128>
Cint32_tRowMajorRowMajor

SpTensorOp 16-by-8-by-128.

OperandElementGMEM LayoutSMEM Layout
Aint4b_tRowMajorRowMajorTensorOpCrosswise<4, 256>
Bint4b_tColumnMajorColumnMajorTensorOpCrosswise<4, 256>
Cint32_tRowMajorRowMajor

Warp-level Matrix Multiply with CUDA WMMA API

The following table summarizes supported warp level shapes for each WmmaTensorOp instruction.

Opcode ClassInstruction ShapeWarp Shapes
WmmaTensorOp16-by-16-by-1632x32x16, 32x64x16, 64x32x16
WmmaTensorOp8-by-32-by-1632x32x16, 32x64x16, 64x32x16
WmmaTensorOp32-by-8-by-1632x32x16, 32x64x16, 64x32x16
WmmaTensorOp8-by-8-by-3232x32x32, 32x64x32, 64x32x32, 64x64x32
WmmaTensorOp8-by-8-by-12832x32x128, 32x64x128, 64x32x128, 64x64x128

CUDA exposes warp-level matrix operations in the CUDA C++ WMMA API. The CUDA C++ WMMA API exposes Tensor Cores via a set of functions and types in the nvcuda::wmma namespace. The functions and types in nvcuda::wmma provide target-independent APIs and implement architecture-specific tensor operation using TensorOp instruction underneath. CUTLASS exposes WMMA API through WmmaTensorOp. The WmmaTensorOp supports canonical shared memory layouts. The following table summarizes the destination shared memory layout that can be targeted by matrix operands. The WMMA API expects that matrices in shared memory loaded by nvcuda::wmma::load_matrix_sync() satisfy 128 bit alignment.

WmmaTensorOp (all matrix sizes and data types).

OperandGMEM LayoutSMEM Layout
ARowMajor, ColumnMajorRowMajor, ColumnMajor
BRowMajor, ColumnMajorRowMajor, ColumnMajor
CRowMajor, ColumnMajorRowMajor, ColumnMajor

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