main-apidocs-erlang-estdlib-serial-underscore-dist-underscore-controller.md
Distribution controller for serial (UART) connections.
Behaviours: gen_server.
This module manages the serial link for the Erlang distribution protocol. It is used by serial_dist and follows the same pattern as socket_dist_controller.
All packets on the wire use the following frame format:
\<\<16#AA, 16#55, Length:LenBits, Payload:Length/binary, CRC32:32\>\>
where LenBits is 16 during the handshake phase and 32 during the data phase. CRC32 covers the Length and Payload bytes.
The receiver scans for the <<16#AA, 16#55>> sync marker, reads the length, validates against a maximum frame size (to reject false sync matches), then verifies the CRC32. On CRC failure, the connection is torn down (no retry/ACK mechanism).
During the handshake phase, send/2 and recv/3 are called synchronously.
After handshake_complete/3, the controller switches to asynchronous mode: a dedicated reader process continuously reads from the UART and forwards data to the controller, which reassembles framed distribution packets and feeds them to erlang:dist_ctrl_put_data/2.
| address/2 | | | code_change/3 | | | getll/1 | | | getstat/1 | | | handle_call/3 | | | handle_cast/2 | | | handle_info/2 | | | handshake_complete/3 | | | init/1 | | | recv/3 | Synchronous receive during handshake. | | scan_frame/2 | Scan a buffer for a framed packet. | | send/2 | Synchronous send during handshake. | | send_preamble/2 | | | setopts_post_nodeup/1 | | | setopts_pre_nodeup/1 | | | start/2 | Start a controller for an outgoing (setup) connection. | | start/3 | Start a controller for an incoming (accept) connection with initial data already read from the UART by the accept loop. | | supervisor/2 | | | terminate/2 | | | tick/1 | |
address(Controller, Node) -> any()
code_change(OldVsn, State, Extra) -> any()
getll(Controller) -> any()
getstat(Controller) -> any()
handle_call(X1, From, State) -> any()
handle_cast(X1, State) -> any()
handle_info(X1, State0) -> any()
handshake_complete(Controller, Node, DHandle) -> any()
init(X1) -> any()
recv(Controller, Length, Timeout) -> any()
Synchronous receive during handshake. Reads one complete framed packet (with 16-bit length field) from UART.
scan_frame(Buffer::binary(), LenBits::16 | 32) -> {ok, binary(), binary()} | {need_more, binary()} | {crc_error, binary()}
Scan a buffer for a framed packet.
LenBits is 16 (handshake) or 32 (data phase). Returns: {ok, Payload, Rest} - a complete, CRC-verified frame was found {need_more, TrimmedBuffer} - no complete frame yet {crc_error, Rest} - a frame was found but CRC did not match
send(Controller, Data) -> any()
Synchronous send during handshake. Wraps data in a framed packet with 16-bit length field.
send_preamble(UartMod, Uart) -> any()
setopts_post_nodeup(Controller) -> any()
setopts_pre_nodeup(Controller) -> any()
start(Uart, UartMod) -> any()
Start a controller for an outgoing (setup) connection.
start(Uart, UartMod, InitialData) -> any()
Start a controller for an incoming (accept) connection with initial data already read from the UART by the accept loop.
supervisor(Controller, Pid) -> any()
terminate(Reason, State) -> any()
tick(Controller) -> any()